1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device including a field effect transistor and a method for manufacturing the same.
2. Description of the Related Art
In a method for manufacturing a semiconductor device, a damascene process is generally used as a method of forming wiring.
In the damascene process, for example, a trench for a gate electrode is formed in an insulating film on a substrate, and a conductive material is deposited to fill the trench for a gate electrode and then removed from the outside the trench by CMP (Chemical Mechanical Polishing), leaving the conductive material in the trench for a gate electrode to form wiring.
MOSFET (metal-oxide-semiconductor field effect transistor; referred to as a “MOS transistor” hereinafter) which is a basic element of a semiconductor device is increasingly miniaturized with advances in miniaturization and increase in integration of semiconductor devices. Therefore, the gate length and the thickness of a gate insulating film are decreased in association with scaling.
A SiON insulating film used as a gate insulating film causes large leakage after the 32-nm generation, and thus it is difficult to use the SiON insulating film as a gate insulating film.
Therefore, there is studied a method using a high-dielectric-constant film (so-called High-k film) capable of being increased in physical film thickness as a gate insulating film material.
Since the High-k film generally has low heat resistance, a gate insulating film is desirably formed after diffusion heat treatment of a source-drain region in which high-temperature treatment is performed.
As a method for permitting this procedures, a damascene gate process of forming a gate electrode of a MOS transistor using the Damascene process is generally used.
Japanese Unexamined Patent Application Publication No. 2005-303256 discloses a method for forming a MOS transistor having a source-drain region provided with an extension region using the damascene gate process.
In this method, for example, a dummy gate insulating film and a dummy gate electrode are formed on an active region of a semiconductor substrate, offset spacers composed of silicon nitride are formed on both sides of the dummy insulating film on the substrate, and the semiconductor substrate is implanted with ions using the dummy gate electrode and the offset spacers as a mask to form extension regions.
Next, sidewall spacers are formed on both sides of the offset spacers on the substrate, and the semiconductor substrate is implanted with ions using the dummy gate electrode, the offset spacers, and the sidewall spacers as a mask to form source-drain regions.
As described above, the source-drain regions each provided with the extension region are formed.
Next, an interlayer insulating film is formed over the entire surface to cover the dummy gate electrode, the top surface is polished until the surface of the dummy gate electrode is exposed, and then the dummy gate electrode and the dummy gate insulating film are removed by etching to form a trench for a gate electrode.
Next, a gate insulating film is formed at the bottom of the trench for a gate electrode, and then a gate electrode is formed on the gate insulating film to fill the trench for a gate electrode.
As described above, a MOS transistor is formed using the damascene process.
When the trench for a gate electrode is formed, the dummy gate insulating film is preferably removed by wet etching in order to prevent damage to the substrate. Therefore, in Japanese Unexamined Patent Application Publication No. 2005-303256, the offset spacers are composed of silicon nitride in order to prevent the offset spacers from being removed by wet etching.
Although the offset spacers can be prevented from being removed by the wet etching, a parasitic capacity between the gate electrode and the source-drain regions is increased because the dielectric constant of silicon nitride is higher than that of silicon oxide. This causes deterioration in MOS transistor characteristics.